The present invention relates to a nonvolatile memory system, and more particularly to a technique that can be effectively applied to, for instance, a flash memory card and a flash disk compatible with a hard disk.
Rewriting of stored information in an electrically rewritable nonvolatile memory, typically a flash memory, gives rise to electrical stresses in memory cells, and the characteristics of the memory cells deteriorate with an increase in the count of rewrites. It is therefore a usual practice to predetermine the number of rewrites up to which the performance of the nonvolatile memory can be guaranteed. Rewrites may concentrate on some of the data blocks, and there are provided techniques by which any data block which has reached the permissible limit of rewrites is replaced with an unused memory block in an alternative area (see Patent References 1 and 2).
There also is available a technique by which the number of corrections by EEC in each data block is counted, and any data block whose correction count has reached a certain number is replaced with an unused memory block in an alternative area (see Patent Reference 3).
Furthermore, since any data block on which writes have concentrated would significantly deteriorate in performance, there also is a technique by which, when data and address rewrites have reached a certain count, the pertinent area is automatically replaced with an area where the number of rewrites is smaller, and the rewritable life of the nonvolatile memory is thereby extended. For instance, if the number of rewrites surpasses a predetermined level, address allocation in the data block will be altered (see Patent Reference 4). Or if the number of ECC errors surpasses a predetermined level, address allocation in the data block will be altered (see Patent Reference 5).    Patent Reference 1: Japanese Unexamined Patent Publication No. Hei 08 (1996)-96589    Patent Reference 2: Japanese Unexamined Patent Publication No. 2001-229069    Patent Reference 3: WO 01/22232    Patent Reference 4: U.S. Pat. No. 5,434,825    Patent Reference 5: U.S. Pat. No. 5,583,812